Variable-length instruction buffer management
US10572252B2 · kind B2 · utility
3Cited by
46References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2016 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Dec 16, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.