Patent · US Active

Switching between thread mode and transaction mode for a set of registers

US10572299B2 · kind B2 · utility

0Cited by

1References

14Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Stephan Diestelhorst · Dresden, DE
Matthew James Horsnell · Cambridge, GB
Guy Larri · Cambridge, GB

Key dates

Filing date	Nov 24, 2015
Grant date	Feb 25, 2020
Priority date	—
Expiry date	Mar 29, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3867
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.