Shared processing of a packet flow by multiple cores
US10572400B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Oct 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.