Patent · US Active

Enabling automatic staging for nets or net groups with VHDL attributes

US10572618B2 · kind B2 · utility

0Cited by

9References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Manuel Beck · Bietigheim-Bissingen, DE
Florian Braun · San Antonio, US
Lukas Dällenbach · Altdorf, DE
Heinz Josef Hemmes · Holzgerlingen, DE
Marvin von der Ehe · Herrenberg, DE

Key dates

Filing date	Nov 28, 2017
Grant date	Feb 25, 2020
Priority date	—
Expiry date	Apr 27, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.