Shift register unit and driving method thereof, gate driving circuit and display device to reduce drift of potential of a pull-down node when the potential is risen
US10573224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2016 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2354/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a shift register unit, including a pull-up node, a pull-down node, a low-level signal terminal, a second clock signal terminal and a pull-down module, the second clock signal terminal supplies a high-level signal during an input sub-period and a pull-down sub-period, the pull-down module is connected to the pull-up node, the pull-down node, an output terminal of the shift register unit and the low-level signal terminal, the shift register unit further includes a discharging module, which is configured to make the pull-down node and the low-level signal terminal be connected in a conducting path during the input sub-period, and both the pull-up node and the output terminal of the shift register unit are connected with the low-level signal terminal in conducting paths during the input sub-period and the pull-down sub-period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.