Displays with luminance adjustment circuitry to compensate for gate line loading variations
US10573236B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2019 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/16
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may have an array of pixels. Due to the presence of a notch in the display, the display may have some rows that are shorter than other rows in the display, and accordingly different gate line loading. To account for the gate line loading variations, the display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. In other arrangement, luminance adjustment circuitry may receive image data and generate corresponding compensated image data to account for gate line loading variations between rows of pixels in the display. The image data may be compensated based on the location of the pixel, the gray level of the image data, the display brightness, and/or temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.