Display device which prevents formation of a parasitic capacitor in a pixel
US10573243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Apr 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/805
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device includes: a plurality of pixels substantially in a matrix form including a plurality of pixel columns in a first direction and a plurality of pixel rows in a second direction intersecting the first direction; a plurality of data lines connected to the pixel columns, respectively; a plurality of scan lines extending in the second direction; and a power line which supplies a driving power voltage to the pixels. Each of the data lines includes a first sub-data line disposed at a side of a corresponding pixel column, and a second sub-data line disposed at an opposite side of the corresponding pixel column, and each of the pixels includes a first transistor and a display element connected to the first transistor, where the power line overlaps with at least a portion of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.