Memory devices and memory packages
US10573401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Aug 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06586
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of receivers that each include a first input terminal coupled to one pin of a plurality of input/output pins. The memory devices further includes a transmitter having an output terminal coupled to the first input terminals of the plurality of receivers. The memory device further includes a control circuit configured to control the transmitter to output a particular test signal. The plurality of receivers are each configured to generate output data based on receiving the particular test signal from the transmitter. The control circuit is further configured to adjust the plurality of receivers based on the output data generated by the plurality of receivers and received at the control circuit from the plurality of receivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.