Semiconductor structure and fabrication method thereof
US10573563B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 5, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Jan 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.