Semiconductor device including overlay patterns
US10573633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.