Integrated circuit having vertical transistor and semiconductor device including the integrated circuit
US10573643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Aug 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.