Integrated semiconductor device and method for manufacturing the same
US10573645B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Sep 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.