Stacked CMOS image sensor
US10573679B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Jun 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked complementary metal oxide semiconductor (CMOS) image sensor includes: a first semiconductor chip in which a plurality of pixels are in an upper area in a two-dimensional array structure and a first wiring layer is in a lower area; and a second semiconductor chip in which a second wiring layer is arranged in an upper area and logic elements are in a lower area, wherein the first semiconductor chip is coupled to the second semiconductor chip through a connection between a first metal pad in a first pad insulating layer in a lowermost portion of the first wiring layer and a second metal pad in a second pad insulating layer in an uppermost portion of the second wiring layer, and wherein a metal-insulator-metal (MIM) capacitor is in at least one of the first pad insulating layer and the second pad insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.