Successive approximation register analog-to-digital converter and associated control method
US10574248B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/202
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.