Hybrid flash architecture of successive approximation register analog to digital converter
US10574254B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.