Physical layer circuitry for multi-wire interface
US10574431B2 · kind B2 · utility
0Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A physical layer circuitry (PHY) includes: N signal pads, a four-signal physical medium attachment sublayer (PMA) and M shielding pads. The N signal pads include at least four signal pads. The four-signal PMA is coupled to the four signal pads. The M shielding pads include at least one first shielding pad that is coupled to the four-signal PMA. Additionally, the first shielding pin is located between a second signal pad of the four signal pads and a third signal pad of the four signal pads; and M and N are positive integers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.