Integrated circuit device and system on a chip (SOC) for reducing boot time
US10579116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.