Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor
US10579387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technical solutions are described for executing one or more out-of-order (OoO) instructions by a processing unit. The execution includes detecting, by a load-store unit (LSU), a load-hit-store (LHS) in an out-of-order execution of the instructions, the detecting based only on effective addresses. The detecting includes determining an effective address associated with an operand of a load instruction. The detecting further includes determining whether a store instruction entry using said effective address to store a data value is present in a store reorder queue, and indicating that an LHS has been detected based at least in part on determining that store instruction entry using said effective address is present in the store reorder queue. In response to detecting the LHS, a store forwarding is performed that includes forwarding data from the store instruction to the load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.