System on a chip hardware block for translating commands from processor to read boot code from off-chip non-volatile memory device
US10579391B2 · kind B2 · utility
1Cited by
8References
14Claims
0Family size
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Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Jul 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Translation of boot code read request commands from an on-board processor of a system on a chip (SoC) from a bus protocol (e.g., advanced high-performance bus (AHB) protocol) into a sequence of commands understandable by a serial interface of the SoC to read boot code from an off-board (e.g., flash or other non-volatile) memory device. The serial interface of the memory device may include a relatively low pin count (e.g., 5 pins) and boot code of the memory device may be modified after tape-out of the SoC free of necessitating a subsequent tape-out of the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.