Circuit and method of power on initialization for configuration memory of FPGA
US10579393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2015 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Aug 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i−1)th time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.