Task latency debugging in symmetric multiprocessing computer systems
US10579499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.