Reducing overhead of managing cache areas
US10579529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | May 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache slot in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache slot is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes converting the local cache slot into a global cache slot in response to one of the processors performing a write operation to the specific portion of non-volatile storage, wherein the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different ones of the processors may be placed on different directors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.