Selective conditional stall for hardware-based circuit design verification
US10579776B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various aspects of the present disclosed technology relate to techniques for selective conditional stall for speeding up hardware-based circuit verification. A path-breaking circuit device is inserted into a location of a design path configured to generate a stall signal indicating whether a change of signal between a pair of neighboring clock cycles of a clock signal is detected at the location. The stall signal is used to directly or indirectly suppress, when the change of signal between the pair of neighboring clock cycles is detected, the next state updating for state element models in the hardware model of circuit design. The design path is usually the critical design path. The insertion location is usually selected to be a location where the signal does not change frequently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.