Tile-based low-resolution depth storage
US10580151B2 · kind B2 · utility
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Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Feb 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for generating, with a graphics processing unit (GPU), depth values for pixels of a tile. The tile is one of a plurality of tiles of a frame. The GPU may store a first number of the depth values for the pixels in a tile memory internal to the GPU. The tile memory is configured to store image content for the tile of the frame. The GPU may write a second number of the depth values stored in the tile memory to a system memory. The second number is less than the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.