Array substrate and display panel
US10580803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/40
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate and a display panel are provided. The array substrate includes a non-display area and a display area. The non-display area includes a first non-display area and a second non-display area, and the display area includes a normal display area and a wiring area. The normal display area is surrounded by the first non-display area, the wiring area is surrounded by the normal display area, and the second non-display area is surrounded by the wiring area. The second non-display area comprises an opening area. In the solution, since the number of data lead lines in the same layer in the wiring area is reduced, a line distance between adjacent data lead lines is increased, thereby reducing coupling capacitance between adjacent data lead lines arranged in the same layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.