Memory device
US10580964B2 · kind B2 · utility
2Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Mar 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic antiferromagnetic layer, and upper electrode formed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.