Magnetic memory device
US10580965B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 4, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of magnetic tunnel junction structures is arranged in rows and columns on a substrate. A plurality of top electrodes is disposed on the plurality of magnetic tunnel junction structures, respectively. A plurality of bit lines is disposed on the substrate. One of the plurality of bit lines is disposed between two magnetic tunnel junction structures, adjacent to each other, of the plurality of magnetic tunnel junction structures. A top surface of each of the plurality of bit lines is disposed at substantially the same level as a top surface of each of the plurality of top electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.