External and dual ramp clock synchronization
US10581416B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2019 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.