Fault tolerant low leakage switch
US10581423B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2019 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Jan 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.