Dual-rail transceiver with improved signal-to-noise ratio for differential high-speed links
US10581645B1 · kind B1 · utility
13Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2019 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | May 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.