System and method for PAM-4 transmitter bit equalization for improved channel performance beyond 32 Gbps
US10581652B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | May 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03343
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial data channel includes a transmitter that encodes serial data using a quaternary PAM-4 scheme, wherein the four PAM-4 signal levels include two balanced pairs of differential signal levels. The channel includes a de-emphasis circuit that determines that first and second symbols are in a first PAM-4 state, that a third symbol is in a second PAM-4 state, and provides a first de-emphasis to a voltage level of the second symbol in response to determining that the third symbol is represented as the second state. The de-emphasis circuit further determines that fourth and fifth symbols are in the second state, that a sixth symbol is in the first state, and provides a second de-emphasis to a voltage level of the fifth symbol in response to determining that the sixth symbol is represented as the first state. The first de-emphasis and the second de-emphasis represent different de-emphasis levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.