Packet scheduling in a switch for reducing cache-miss rate at a destination network node
US10581762B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2017 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Mar 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/568
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network switch includes switch circuitry and multiple ports. The ports are configured to communicate with a communication network. The switch circuitry is configured to receive via the ports multiple packets, which are destined to a destination network node and which specify attributes used by the destination network node as cache keys for on-demand fetching of context items into a cache memory of the destination network node, to control a rate of fetching the context items into the cache memory at the destination network node, by ordering the received packets in a sequence, based on the attributes of the respective packets, using an ordering criterion that aims to place packets that access a common context item in proximity to one another in the sequence, and to forward the received packets to the destination network node, via the ports, in accordance with the ordered sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.