Process-induced excursion characterization
US10585049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2019 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system includes a controller with one or more processors and memory configured to store one or more sets of program instructions. The one or more processors are configured to execute the one or more sets of program instructions. The one or more sets of program instructions are configured to cause the one or more processors to apply filtering to a semiconductor wafer map; separate the filtered semiconductor wafer map into a plurality of dies; generate a set of die comparison statistics for the plurality of dies; generate at least one excursion map by applying at least one inspection threshold to the set of die comparison statistics; and detect at least one excursion within the at least one excursion map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.