Array substrate and driving method and manufacturing method thereof
US10585320B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The embodiment of the present disclosure discloses an array substrate. The array substrate comprises: a base, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a common electrode line, and a plurality of pixel units. Each of the pixel units comprises: a first electrode, a second electrode, a switch transistor, a shared transistor and a shared capacitor. The switch transistor has a first terminal coupled to the second electrode, a second terminal coupled to one of the plurality of data lines, a bottom gate coupled to one of the plurality of first scanning lines, and a top gate coupled to one of the plurality of second scanning lines, and is configured to transfer a data signal of the data line to the second electrode under the control of a first scanning signal and a second scanning signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.