Clock circuitry for functionally safe systems
US10585449B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2019 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Jan 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.