Patent · US Active

Memory block erasure

US10585619B1 · kind B1 · utility

4Cited by

4References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Martin Bernhard Schmidt · Stuttgart, DE
Peter Altevogt · Ettlingen, DE
Wolfgang Gellerich · Eppelheim, DE
Juergen Pille · Stuttgart, DE

Key dates

Filing date	Nov 15, 2018
Grant date	Mar 10, 2020
Priority date	—
Expiry date	Nov 15, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of memory block erasure are described herein. An aspect includes determining a first word line set consisting of a first plurality of word lines. Another aspect includes activating the first plurality of word lines, such that a respective memory cell that is connected to each of the first plurality of word lines is erased by the activation of the first plurality of word lines. Another aspect includes determining a second word line set, wherein the second word line set consists of the first word line set and a second plurality of word lines. Another aspect includes simultaneously activating the first plurality of word lines and the second plurality of word lines, such that a respective memory cell that is connected to each of the second plurality of word lines is erased by the activation of the first plurality of word lines and the second plurality of word lines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.