Patent · US Active

Operating different processor cache levels

US10585797B2 · kind B2 · utility

1Cited by

8References

4Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Simon H. Friedmann · Eppelheim, DE
Christian Jacobi · West Park, US
Markus Kaltenbach · Holzgerlingen, DE
Ulrich Mayer · Weißenhorn, DE
Anthony Saporito · Highland, US

Key dates

Filing date	Jul 14, 2017
Grant date	Mar 10, 2020
Priority date	—
Expiry date	Jul 14, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/507
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer implemented method to operate different processor cache levels of a cache hierarchy for a processor with pipelined execution is suggested. The cache hierarchy comprises at least a lower hierarchy level entity and a higher hierarchy level entity. The method comprises: sending a fetch request to the cache hierarchy; detecting a miss event from a lower hierarchy level entity; sending a fetch request to a higher hierarchy level entity; and scheduling at least one write pass.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.