SSD architecture for FPGA based acceleration
US10585843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream fil…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.