Secure stack overflow protection via a hardware write-once register
US10586038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2017 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for providing stack overflow protection on a system on chip via a hardware write-once register. An exemplary embodiment of an system on chip comprises a hardware write-once register, a boot processor, and one or more processor subsystems. The boot processor is configured to execute a read only memory (ROM) image which initializes the hardware write-once register with a first numeric value in response to the system on chip being powered on. The one or more processor subsystems have an associated software image configured to use the first numeric value in the hardware write-once register as a stack canary value to combat stack overflow attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.