Semiconductor device and semiconductor-device manufacturing method
US10586823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line. Then, by embedding copper in the hole, the through-silicon via made of the copper can be created. After the through-silicon via has been connected to the line made of aluminum through the member which is a connection area, the connection area is alloyed in a thermal treatment in order to electrically connect the through-silicon via to the line. Thus, it is possible to reduce variations of a resistance between the through-silicon via and the line and also improve wiring reliability as well. The present technology can be applied to a semiconductor device and a method for manufacturing the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.