Light emitting diode memory
US10586831B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2019 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Jan 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A light emitting diode memory includes a substrate, a tunneling structure, a current spreading layer, a first electrode layer and a second electrode layer. The tunneling structure is formed on the substrate. The tunneling structure includes first, second and third material layers. The current spreading layer is formed on the tunneling structure. The first electrode layer is formed on the substrate. The second electrode layer is formed on the current spreading layer. When a bias voltage applied to the first electrode layer and the second electrode layer is higher than a reset voltage, the light emitting diode memory is in a reset state. When the bias voltage is lower than a set voltage, the light emitting diode memory is in a set state. When the bias voltage is higher than a turn-on voltage, the light emitting diode memory emits a light beam.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.