DV/DT self-adjustment gate driver architecture
US10587262B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2019 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Mar 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate driver circuit includes a gate driver and a sensing circuit. The gate driver is configured to generate an on-current during a plurality of turn-on switching events to drive a transistor, where a voltage across the transistor changes from a first value to a second value with a slope during the plurality of turn-on switching events, where the slope is of either an active type dependent on an amplitude of the on-current or a passive type. The sensing circuit determines whether the slope during a first turn-on switching event is the active type or the passive type, and regulates the amplitude of the on-current during a second turn-on switching event that is subsequent to the first turn-on switching event if the slope is the active type and to maintain the amplitude of the on-current as unchanged during the second turn-on switching event if the slope is the passive type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.