Signal processing apparatus and method
US10591953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2016 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.