Efficient instruction processing for sparse data
US10592252B2 · kind B2 · utility
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9References
14Claims
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Key dates
| Filing date | Dec 31, 2015 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.