Adaptive timeout mechanism
US10592322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2017 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus includes a processing logic circuit configured to perform transactions requested by a requester device, and a timeout prevention logic coupled to the processing logic circuit. The timeout prevention logic includes a timeout logic and a moderation logic. The timeout logic is configured to, when the processing logic circuit fails to complete a particular transaction requested by the requester device within a reconfigurable time period, generate a timeout event and complete the particular requested transaction. The moderation logic is configured to determine a number of timeout events generated by the timeout logic during a monitoring time period, and set the reconfigurable time period based on the number of timeout events generated by the timeout logic during the monitoring time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.