Patent · US Active

Efficient mechanism of fault qualification using formal verification

US10592624B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Synopsis, Inc. · US

Inventors

Sandeep Jana · Bengaluru, IN
Arunava Saha · Dublin, US
Pratik Mahajan · Damoh, IN
Per M. Bjesse · Portland, US
Alfred Koelbl · Dachau, DE

Key dates

Filing date	Jun 1, 2018
Grant date	Mar 17, 2020
Priority date	—
Expiry date	Aug 1, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.