Information protection method and device based on a plurality of sub-areas for MCU chip
US10592644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2015 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information protection method and device based on a plurality of sub-areas for an MCU chip, the MCU chip comprises an instruction bus, a data bus, a flash controller and a user area of a flash memory, the method comprises: determining a preceding sub-area when the instruction bus accesses the user area; entering corresponding preceding sub-area working state; determining the current sub-area when the instruction bus accesses the user area; when the preceding sub-area is inconsistent with the current sub-area, entering the transition state; determining whether the duration of the transition state reaches the preset waiting time; if yes, entering the corresponding current sub-area working state. The information protection method and device prevent the cooperative companies which develop the program together from stealing program from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.