Security arrangement for integrated circuits using arrays of capacitive elements
US10593632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Sep 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed that comprises a first security arrangement that overlaps a plurality of electronic components arranged within one or more layers. The first security arrangement comprises a first conductive layer patterned as a first array of a plurality of first conductive elements, and a second conductive layer separated from the first conductive layer by a dielectric layer. The second conductive layer patterned as a second array of a plurality of second conductive elements, and the first array and the second array collectively form a plurality of capacitive elements. The apparatus further comprises monitoring circuitry coupled with the first security arrangement and configured to detect a change in a capacitance of a first capacitive element of the plurality of capacitive elements, and determine, based on a location of the first capacitive element within the first array, whether to perform a predefined security action.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.