Array substrate and fabricating method thereof
US10593807B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6736
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate is disclosed, including a thin film transistor including a substrate, a first gate, a first insulating layer, an active layer, a source, a drain, a second and a third insulating layers, and a second gate. The first gate is disposed on the substrate, the first insulating layer is disposed on the first gate and the substrate, and the active layer is disposed on the first insulating layer, the source and the drain disposed on the active layer form a channel with the active layer, the second insulating layer, the third insulating layer, and the second gate are sequentially disposed in the channel region, a distance between an edge of the second insulating layer and the source and the drain is greater than a distance between an edge of the third insulating layer and the source and the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.