Current limiting control method and device for three-level inverter
US10594208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | May 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/53871
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A current limiting control method for a three-level inverter, comprising the following steps: S1. when a current output from a bridge arm is greater than or equal to a current limiting threshold and a received overcurrent signal is enabled, first turning off the main switch transistors and then turning off the auxiliary switch transistors; S2. when the current output from the bridge arm drops to lower than the current limiting threshold and the received overcurrent signal is disabled, turning on the auxiliary switch transistors; S3. when the received overcurrent signal is disabled and a next PWM effective edge of the main switch transistors arrives, turning on the main switch transistors. The present invention relates also to a current limiting control device for a three-level inverter. By implementing the present invention, it is possible to ensure voltage waveform quality and reduce switching loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.